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ARM: zynq: slcr: Dont modify the reserved bits
authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Tue, 28 Oct 2014 05:52:19 +0000 (11:22 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 26 Jan 2015 07:55:57 +0000 (08:55 +0100)
commitf60c6fbbc658201f968a22addff7dd1acbe5eaca
tree36232fa5b868ef1572a9da4baebe235c84b5ac84tree | snapshot
parent3ad87ca18203f8b0de0e30b7c12d2ffadf2d8553commit | diff
ARM: zynq: slcr: Dont modify the reserved bits

Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/cpu/armv7/zynq/slcr.c diff | blob | history
Broadcom-s U-Boot