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(parent: 8e29eba) | patch
powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
authorYork Sun <yorksun@freescale.com>
Wed, 2 Mar 2011 22:24:11 +0000 (14:24 -0800)
committerKumar Gala <galak@kernel.crashing.org>
Sat, 5 Mar 2011 16:13:50 +0000 (10:13 -0600)
commitf5b6fb7c1b988cdec8db9e96dd05d1df46c22e6b
tree8d9bac65135dedd1eb7c02308a1922057747aa32tree | snapshot
parent8e29ebabf825ee0c85cb0c93d6aa495cc54811abcommit | diff
powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c diff | blob | history
Broadcom-s U-Boot