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(parent: 4fbd8d1) | patch
dt-bindings: misc: Add Tegra186 MISC registers bindings
authorThierry Reding <treding@nvidia.com>
Mon, 26 Jun 2017 15:33:12 +0000 (17:33 +0200)
committerThierry Reding <treding@nvidia.com>
Wed, 13 Dec 2017 11:42:30 +0000 (12:42 +0100)
commitf580fd3f9d78cf0425ab98950796c578d8a82167
tree5ab1276160226e5cae7291f12c822fcb9bec656atree | snapshot
parent4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323commit | diff
dt-bindings: misc: Add Tegra186 MISC registers bindings

The MISC register block found on Tegra186 SoCs contains registers that
can be used to identify a given chip and various strapping options.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt [new file with mode: 0644] blob
John Crispins staging tree