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(parent: c4fc9e5) | patch
spi: tegra114: configure dma burst size to fifo trig level
authorSowjanya Komatineni <skomatineni@nvidia.com>
Wed, 27 Mar 2019 05:56:29 +0000 (22:56 -0700)
committerMark Brown <broonie@kernel.org>
Mon, 1 Apr 2019 08:39:42 +0000 (15:39 +0700)
commitf4ce428c41fb22e3ed55496dded94df44cb920fa
tree7a792e6e31c95ca8d9acd3512a2e31d7256feba7tree | snapshot
parentc4fc9e5b28ff787e35137c2cc13316bb11d7657bcommit | diff
spi: tegra114: configure dma burst size to fifo trig level

Fixes: Configure DMA burst size to be same as SPI TX/RX trigger levels
to avoid mismatch.

SPI FIFO trigger levels are calculated based on the transfer length.
So this patch moves DMA slave configuration to happen before start
of DMAs.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-tegra114.c diff | blob | history
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