[ARM] mv78xx0: enable eth2/eth3 on the mv78xx0 A0 development board

[ARM] mv78xx0: enable eth2/eth3 on the mv78xx0 A0 development board

The A0 revision of the mv78xx0 development board has four ethernet
ports, with PHY IDs 8-11, whereas the Z0 version has two, with PHY
addresses 8-9.  This patch configures the third and fourth ethernet
port to use the PHY addresses on the A0 board to enable use of those
ports -- if we are running on a Z0 board, the ge10/11 setup code in
common.c will force these back to PHYless mode.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>