drm/i915/gvt: Correct the privilege shadow batch buffer address
authorfred gao <fred.gao@intel.com>
Thu, 15 Mar 2018 05:21:10 +0000 (13:21 +0800)
committerZhenyu Wang <zhenyuw@linux.intel.com>
Thu, 15 Mar 2018 07:06:26 +0000 (15:06 +0800)
commitef75c685869ea2059f85855a7dc00148a704c36c
treea06433a00f8ce0f55fa9ed90c6a0f2f7c949f171
parentfa3dd623e559e8e7004179f9594b090318df0d05
drm/i915/gvt: Correct the privilege shadow batch buffer address

Once the ring buffer is copied to ring_scan_buffer and scanned,
the shadow batch buffer start address is only updated into
ring_scan_buffer, not the real ring address allocated through
intel_ring_begin in later copy_workload_to_ring_buffer.

This patch is only to set the right shadow batch buffer address
from Ring buffer, not include the shadow_wa_ctx.

v2:
- refine some comments. (Zhenyu)
v3:
- fix typo in title. (Zhenyu)
v4:
- remove the unnecessary comments. (Zhenyu)
- add comments in bb_start_cmd_va update. (Zhenyu)

Fixes: 0a53bc07f044 ("drm/i915/gvt: Separate cmd scan from request allocation")
Cc: stable@vger.kernel.org # v4.15
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Yulei Zhang <yulei.zhang@intel.com>
Signed-off-by: fred gao <fred.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
drivers/gpu/drm/i915/gvt/cmd_parser.c
drivers/gpu/drm/i915/gvt/scheduler.c
drivers/gpu/drm/i915/gvt/scheduler.h