fsl-ddr: Fix the turnaround timing for TIMING_CFG_4
authorDave Liu <daveliu@freescale.com>
Fri, 5 Mar 2010 04:22:00 +0000 (12:22 +0800)
committerKumar Gala <galak@kernel.crashing.org>
Wed, 7 Apr 2010 05:07:23 +0000 (00:07 -0500)
commitec145e87b80f6764d17a6b0aebf521fe758c3fdc
tree41e5ea01cfc6d023c4789bdf759f447c7cc43dad
parentab467c512e79dbd14f02352655f054a4304c457e
fsl-ddr: Fix the turnaround timing for TIMING_CFG_4

Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and
OTF case, BL/2 cycles is enough for fixed BL8.
Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2
will improve the memory performance.

Signed-off-by: Dave Liu <daveliu@freescale.com>
cpu/mpc8xxx/ddr/ctrl_regs.c