generic: MIPS: Add barriers between dcache & icache flushes

generic: MIPS: Add barriers between dcache & icache flushes

This fixes spurious boot-errors with some ath79 MIPS 74Kc boards such
as the AC Lite as well as Archer C7 v2.

The missing barrier leads to the icache flush being executed before the
dcache writeback, which results in the CPU executing the dummy infinite
loop in tlbmiss_handler_setup_pgd.

Applying this patch from upstream ensures the dcache is written back
before flushing the icache.

Signed-off-by: David Bauer <mail@david-bauer.net>
(cherry picked from commit 26bc8f68767e1ec6e33a84ef397e4c38d5968462)