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(parent: 13f417f) | patch
arm64: cpufeature: Correct feature register tables
authorSuzuki K Poulose <suzuki.poulose@arm.com>
Tue, 26 Jan 2016 10:58:13 +0000 (10:58 +0000)
committerCatalin Marinas <catalin.marinas@arm.com>
Thu, 25 Feb 2016 10:33:07 +0000 (10:33 +0000)
commite53435031a541762223b03f5e6f0ebd98bdf3501
tree387a50a10af781873d3dc5a69e0a898e3d1a2ce7tree | snapshot
parent13f417f3b83f78de402f1674aa9009f778d768c3commit | diff
arm64: cpufeature: Correct feature register tables

Correct the feature bit entries for :
  ID_DFR0
  ID_MMFR0

to fix the default safe value for some of the bits.

Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/kernel/cpufeature.c diff | blob | history
John Crispins staging tree