spi: spi-sh-msiof: round up div to fix freq calculation
authorTakashi Yoshii <takasi-y@ops.dti.ne.jp>
Sun, 1 Dec 2013 18:19:13 +0000 (03:19 +0900)
committerMark Brown <broonie@linaro.org>
Mon, 2 Dec 2013 12:48:05 +0000 (12:48 +0000)
commite4d313ff79a8b5622a8c4954ba37c6564fa922c4
tree6b2d521cd48d521f6b7f37ea9b2e27dfe0ee4350
parent6ce4eac1f600b34f2f7f58f9cd8f0503d79e42ae
spi: spi-sh-msiof: round up div to fix freq calculation

Truncation on integer division in sh_msiof_spi_set_clk_regs()
results in insufficient transfer frequency (> max_speed_freq).

For example, source 52MHz, required max 6MHz
 52/6 = 8.6 --> 8, then 1/8 table selected,
and result in 52/8 = 6.5 MHz (>6MHz)

Rounding it up is a simple solution.
 52/6 = 8.6 --> 9, then 1/16 table selected,
and result in 52/16 = 3.25 MHz

Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp>
Signed-off-by: Mark Brown <broonie@linaro.org>
drivers/spi/spi-sh-msiof.c