[PATCH] Four level pagetables for ppc64
authorDavid Gibson <david@gibson.dropbear.id.au>
Fri, 5 Aug 2005 09:39:06 +0000 (19:39 +1000)
committerPaul Mackerras <paulus@samba.org>
Mon, 29 Aug 2005 00:53:31 +0000 (10:53 +1000)
commite28f7faf05159f1cfd564596f5e6178edba6bd49
tree45534d2c33bff8b64e3fd155fba55146cb7518e6
parentdecd300b30e499fe6be1bbfc5650fc971de8c1fa
[PATCH] Four level pagetables for ppc64

Implement 4-level pagetables for ppc64

This patch implements full four-level page tables for ppc64, thereby
extending the usable user address range to 44 bits (16T).

The patch uses a full page for the tables at the bottom and top level,
and a quarter page for the intermediate levels.  It uses full 64-bit
pointers at every level, thus also increasing the addressable range of
physical memory.  This patch also tweaks the VSID allocation to allow
matching range for user addresses (this halves the number of available
contexts) and adds some #if and BUILD_BUG sanity checks.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
12 files changed:
arch/ppc64/mm/hash_utils.c
arch/ppc64/mm/hugetlbpage.c
arch/ppc64/mm/imalloc.c
arch/ppc64/mm/init.c
arch/ppc64/mm/slb_low.S
arch/ppc64/mm/tlb.c
include/asm-ppc64/imalloc.h
include/asm-ppc64/mmu.h
include/asm-ppc64/page.h
include/asm-ppc64/pgalloc.h
include/asm-ppc64/pgtable.h
include/asm-ppc64/processor.h