MIPS: math-emu: CLASS.D: Zero bits 32-63 of the result
authorAleksandar Markovic <aleksandar.markovic@imgtec.com>
Mon, 21 Aug 2017 12:24:49 +0000 (14:24 +0200)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 29 Aug 2017 13:21:56 +0000 (15:21 +0200)
commite1231dd6b1cfbed9dfda5de488ce23c2414e1f04
treeaa09df505ad525f042e9fabd4e698afb8163b73d
parent3ec404d88cefbe42d96a46f20f554f8366d64c33
MIPS: math-emu: CLASS.D: Zero bits 32-63 of the result

Fix content of CLASS.D output bits 32-63 to match hardware behavior.

Prior to this patch, bits 32-63 of CLASS.D output were not
initialized, causing different 32-63 bits content of CLASS.D, based on
circumstances. However, the hardware consistently returns all these
bits zeroed. The documentation is not clear whether these bits should
be zero or unpredictable. Since technically "all zero" case still can
be viewed as belonging to "unpredictable" class of results, it is
better to zero bits 32-63.

Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Cc: Douglas Leung <douglas.leung@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@imgtec.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Cc: Raghu Gandham <raghu.gandham@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17142/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/math-emu/cp1emu.c