projects / openwrt / staging / blogic.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 13cf4cf) | patch
riscv: Fixup obvious bug for fp-regs reset
authorGuo Ren <ren_guo@c-sky.com>
Sun, 5 Jan 2020 02:52:14 +0000 (10:52 +0800)
committerPaul Walmsley <paul.walmsley@sifive.com>
Sun, 12 Jan 2020 18:12:44 +0000 (10:12 -0800)
commitdc6fcba72f0435b7884f2e92fd634bb9f78a2c60
treededfd6d441a9e9f2854a7bccc11bbaccc8580c40tree | snapshot
parent13cf4cf030183dd9a8731f3fe32456e83b6c7b68commit | diff
riscv: Fixup obvious bug for fp-regs reset

CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine
ISA Register misa. Every bit:1 indicate a feature, so we should beqz
reset_done when there is no F/D bit in csr_misa register.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
[paul.walmsley@sifive.com: fix typo in commit message]
Fixes: 9e80635619b51 ("riscv: clear the instruction cache and all registers when booting")
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
arch/riscv/kernel/head.S diff | blob | history
John Crispins staging tree