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Documentation: perf: Add documentation for ThunderX2 PMU uncore driver
authorKulkarni, Ganapatrao <Ganapatrao.Kulkarni@cavium.com>
Thu, 6 Dec 2018 11:51:27 +0000 (11:51 +0000)
committerWill Deacon <will.deacon@arm.com>
Thu, 6 Dec 2018 12:29:47 +0000 (12:29 +0000)
commitd6310a3f3396e004bdb7a76787a2a3bbc643d0b7
treed5757f27db38310299eb834ea0c813419b818754tree | snapshot
parent754a58db6a556e6e5f5e32f3e84e7d67b5bf9c8ecommit | diff
Documentation: perf: Add documentation for ThunderX2 PMU uncore driver

The SoC has PMU support in its L3 cache controller (L3C) and in the
DDR4 Memory Controller (DMC).

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
[will: minor spelling and format fixes, dropped events list]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Documentation/perf/thunderx2-pmu.txt [new file with mode: 0644] blob
John Crispins staging tree