projects / openwrt / staging / blogic.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 87a5ffb) | patch
clk: ls1028a: Add clock driver for Display output interface
authorWen He <wen.he_1@nxp.com>
Fri, 13 Dec 2019 08:34:02 +0000 (16:34 +0800)
committerStephen Boyd <sboyd@kernel.org>
Fri, 31 Jan 2020 00:28:07 +0000 (16:28 -0800)
commitd37010a3c162f23e47a11a8f5946dbd974999c42
treec88cfd4d84af3241ddfd743948f6b432aead903atree | snapshot
parent87a5ffb34b475263c3f3d187f776d77178be8eb9commit | diff
clk: ls1028a: Add clock driver for Display output interface

Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY),
as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
integer division and range of the display output pixel clock's 27-594MHz.

Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lkml.kernel.org/r/20191213083402.35678-2-wen.he_1@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/Kconfig diff | blob | history
drivers/clk/Makefile diff | blob | history
drivers/clk/clk-plldig.c [new file with mode: 0644] blob
John Crispins staging tree