i2c: fix bus recovery stop mode timing
authorRussell King <rmk+kernel@armlinux.org.uk>
Sun, 15 Dec 2019 16:39:05 +0000 (16:39 +0000)
committerWolfram Sang <wsa@the-dreams.de>
Thu, 9 Jan 2020 21:21:08 +0000 (22:21 +0100)
commitcf8ce8b80f8bf9669f6ec4e71e16668430febdac
tree8b3afdb2fa09a0a1ae660a53f8799bc3239746f4
parent3b722da6672df8392f9c43d7c7e04bddd81d7e37
i2c: fix bus recovery stop mode timing

The I2C specification states that tsu:sto for standard mode timing must
be at minimum 4us. Pictographically, this is:

SCL: ____/~~~~~~~~~
SDA: _________/~~~~
       ->|    |<- 4us minimum

We are currently waiting 2.5us between asserting SCL and SDA, which is
in violation of the standard. Adjust the timings to ensure that we meet
what is stipulated as the minimum timings to ensure that all devices
correctly interpret the STOP bus transition.

This is more important than trying to generate a square wave with even
duty cycle.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
drivers/i2c/i2c-core-base.c