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(parent: fec9181) | patch
drm/i915: add SSC offsets for SBI access
authorEugeni Dodonov <eugeni.dodonov@intel.com>
Thu, 29 Mar 2012 15:32:34 +0000 (12:32 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 9 Apr 2012 16:04:03 +0000 (18:04 +0200)
commitccf1c867ce049bf27a1f7172f1a91820b3ceb6e5
tree232564a6071668eea6bed1b4765620f00da59ef8tree | snapshot
parentfec9181ca4bd70071807c6839cd73e9346a9e023commit | diff
drm/i915: add SSC offsets for SBI access

Different registers are identified by their target id and offset. To
simplify their programming, they are called as <RegisterName><TargetId>.
For example, SSCCTL register accessed through SBI at target id 6 and
offset 0c is called SBI_SSCCTL6.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
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