rockchip: rk3399: improve the m0 enable flow
authorLin Huang <hl@rock-chips.com>
Mon, 12 Dec 2016 07:18:08 +0000 (15:18 +0800)
committerXing Zheng <zhengxing@rock-chips.com>
Fri, 24 Feb 2017 12:07:44 +0000 (20:07 +0800)
commitca9286c68a8fe408912fc1cd1b1e1789339ce135
treed6463a04643baf6183735cd26391c161cbb81cc2
parenta82ec8145961e57d19cdb71ad9823fd99f7f7c53
rockchip: rk3399: improve the m0 enable flow

This patch do following things:
1. Request hresetn_cm0s_pmu_req first then request
   poresetn_cm0s_pmu_req during M0 enable.
2. Do not diable M0 clock for ddr dvfs.
3. Correct the clk_pmum0_gating_dis bit, it is BIT0 not BIT1
4. do not set/clear hclk_noc_pmu_en in M0 code, it does not relate
   to the M0 clock.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
plat/rockchip/rk3399/drivers/dram/dfs.c
plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
plat/rockchip/rk3399/drivers/pmu/m0_ctl.h
plat/rockchip/rk3399/drivers/pmu/pmu.c