projects / openwrt / staging / blogic.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 930bff8) | patch
[MIPS] Use correct dma flushing in dma_cache_sync()
authorThomas Bogendoerfer <tsbogend@alpha.franken.de>
Tue, 27 Nov 2007 18:31:33 +0000 (19:31 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 29 Jan 2008 10:14:58 +0000 (10:14 +0000)
commitc7c6b39050aed4af913c17970ebfb592bae757fc
treefaaad45cd4b3ef2f582c6b47a5082e9eee2853fdtree | snapshot
parent930bff882296c02ca81db108672ef4ca06c37db5commit | diff
[MIPS] Use correct dma flushing in dma_cache_sync()

Not cache coherent R10k systems (like IP28) need to do real cache
invalidates in dma_cache_sync().

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mm/dma-default.c diff | blob | history
John Crispins staging tree