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(parent: e8688fe) | patch
clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
authorPeng Fan <peng.fan@nxp.com>
Thu, 24 Oct 2019 01:58:37 +0000 (01:58 +0000)
committerShawn Guo <shawnguo@kernel.org>
Fri, 25 Oct 2019 09:06:47 +0000 (17:06 +0800)
commitc332481f62fa2f29af234bf85846268a5a0b173e
treec0b6c85f16bb4757c76d3ecde9a7c1b1dead7a65tree | snapshot
parente8688fe8df7d01f43586b4bb74b2fa92f56c5ee8commit | diff
clk: imx: imx8mm: mark sys_pll1/2 as fixed clock

According Architecture definition guide, SYS_PLL1 is fixed at
800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed
to register the clocks and drop code that could change the rate.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/clk/imx/clk-imx8mm.c diff | blob | history
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