cxl: Fix timebase synchronization status on P9
authorChristophe Lombard <clombard@linux.vnet.ibm.com>
Tue, 20 Feb 2018 13:48:56 +0000 (14:48 +0100)
committerMichael Ellerman <mpe@ellerman.id.au>
Wed, 14 Mar 2018 09:01:18 +0000 (20:01 +1100)
commitc2be663d5307fb9751a562ac664fa78cd7a00e2b
treebda7db5d90520ac164fb3948d49677180201d29c
parent014a32b30e9d81b47ef82b9995b52c3a0c8b4082
cxl: Fix timebase synchronization status on P9

The PSL Timebase register is updated by the PSL to maintain the
timebase.

On P9, the Timebase value is only provided by the CAPP as received the
last time a timebase request was performed.

The timebase requests are initiated through the adapter configuration
or application registers.

The specific sysfs entry "/sys/class/cxl/cardxx/psl_timebase_synced"
is now dynamically updated according the content of the PSL Timebase
register.

Fixes: f24be42aab37 ("cxl: Add psl9 specific code")
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
drivers/misc/cxl/pci.c
drivers/misc/cxl/sysfs.c