drm/i915/icl: do a posting read after irq install
authorDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Wed, 23 Jan 2019 02:32:27 +0000 (18:32 -0800)
committerMika Kuoppala <mika.kuoppala@linux.intel.com>
Wed, 23 Jan 2019 11:56:32 +0000 (13:56 +0200)
commitc25f0c6a0426527134d992bb4782cf5abdf962b6
tree9ca9d36b5f72ea6e2efa3adb6e61482caf1435b2
parenta9dc3395fc8bc460761f853b71971bdc1671560f
drm/i915/icl: do a posting read after irq install

When reading GEN11_GT_INTR_DWx closely after enabling the interrupts
in gen11_irq_postinstall, the returned value is garbage. This can
cause other parts of the setup code (e.g. gen11_reset_one_iir) to
think that there are interrupts to be cleared when there are none.

The garbage value is only seen on the first read done after the enable,
so this looks like a posting issue. Adding a posting read after enabling
the interrupts does indeed fix the problem.

Note that the posting read has been purposely added outside of
gen11_master_intr_enable since the issue has only been observed when the
full interrupt setup is performed.

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190123023227.8117-1-daniele.ceraolospurio@intel.com
drivers/gpu/drm/i915/i915_irq.c