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(parent: f56d9df) | patch
drm/msm/adreno: a5xx: Explicitly program the CP0 performance counter
authorJordan Crouse <jcrouse@codeaurora.org>
Tue, 21 Nov 2017 19:40:57 +0000 (12:40 -0700)
committerRob Clark <robdclark@gmail.com>
Wed, 10 Jan 2018 13:58:42 +0000 (08:58 -0500)
commitc09513cfebd8d936a7aed3c0302104fb47a4a03a
tree00def9b8aa3880725e4a494ba88139e104fb75a8tree | snapshot
parentf56d9df656c41b141399c1edbcc9b0ed048120c2commit | diff
drm/msm/adreno: a5xx: Explicitly program the CP0 performance counter

Even though the default countable for CP0 is CP_ALWAYS_COUNT (0),
program the selector during HW initialization in an effort to be
up front about which counters are programmed and why.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/adreno/a5xx_gpu.c diff | blob | history
John Crispins staging tree