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(parent: e6f0bfc) | patch
drm/i915: set the correct eDP aux channel clock divider on DDI
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Tue, 23 Oct 2012 20:30:05 +0000 (18:30 -0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 26 Oct 2012 08:24:50 +0000 (10:24 +0200)
commitb8fc2f6a18052194c486b407765a4f5e4dca692d
tree1a1db94b0ffb90cd25d65ae8e419acbd6673e8c7tree | snapshot
parente6f0bfc4fb963da9e945ebc6330db9a4d756ba78commit | diff
drm/i915: set the correct eDP aux channel clock divider on DDI

The cdclk frequency is not always the same, so the value here should
be adjusted to match it.

Version 2: call intel_ddi_get_cdclk_freq instead of reading
CDCLK_FREQ, because the register is just for earlier HW steppings.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ddi.c diff | blob | history
drivers/gpu/drm/i915/intel_dp.c diff | blob | history
drivers/gpu/drm/i915/intel_drv.h diff | blob | history
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