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(parent: 86e581e) | patch
RISC-V: Add FP register ptrace support for gdb.
authorJim Wilson <jimw@sifive.com>
Thu, 18 Oct 2018 00:59:05 +0000 (17:59 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 23 Oct 2018 00:38:04 +0000 (17:38 -0700)
commitb8c8a9590e4fde82f8c3ee06a521763e6f21e9c8
treec87efbb682f18144e651ecdfd79d95c71bf26087tree | snapshot
parent86e581e310785782e2025a076dc9a3f5138e5bf3commit | diff
RISC-V: Add FP register ptrace support for gdb.

Add a variable and a macro to describe FP registers, assuming only D is
supported.  FP code is conditional on CONFIG_FPU.  The FP regs and FCSR
are copied separately to avoid copying struct padding.  Tested by hand and
with the gdb testsuite.

Signed-off-by: Jim Wilson <jimw@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
arch/riscv/include/uapi/asm/elf.h diff | blob | history
arch/riscv/kernel/ptrace.c diff | blob | history
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