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(parent: 30ca7c6) | patch
drm/i915: IVB FBC WaFbcDisableDpfcClockGating
authorRodrigo Vivi <rodrigo.vivi@gmail.com>
Thu, 9 May 2013 17:08:38 +0000 (14:08 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 10 May 2013 19:56:48 +0000 (21:56 +0200)
commitb74ea102b746a1e5157d6b0c83f486ad3c6235d1
tree56c2ee79b4ca2c2f1b92e3db9857931168e34c88tree | snapshot
parent30ca7c6f97e266d122b03261f75f530d5c83608bcommit | diff
drm/i915: IVB FBC WaFbcDisableDpfcClockGating

Display register 42020h bit 9 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

v2: RMW to preserve other bits (by Ville)
v3: Fix from Ville: sed &/| at RMW
v4: Too far on sed.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c diff | blob | history
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