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(parent: 40e7bcd) | patch
arm: socfpga: cache: Enable PL310 L2 cache
authorMarek Vasut <marex@denx.de>
Sun, 14 Sep 2014 23:45:14 +0000 (01:45 +0200)
committerMarek Vasut <marex@denx.de>
Mon, 6 Oct 2014 15:46:50 +0000 (17:46 +0200)
commitb5e9b296251f138ef9f9cfc15f408710a24831cd
treef2ea633bcc66ea69c6c5520ded9ccd916e295838tree | snapshot
parent40e7bcdee72830fa51d9e98428f1a61f9126527ecommit | diff
arm: socfpga: cache: Enable PL310 L2 cache

Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
include/configs/socfpga_cyclone5.h diff | blob | history
Broadcom-s U-Boot