mx6: Set shared override bit in PL310 AUX_CTRL register
authorFabio Estevam <fabio.estevam@freescale.com>
Wed, 11 Mar 2015 20:12:12 +0000 (17:12 -0300)
committerStefano Babic <sbabic@denx.de>
Fri, 15 May 2015 17:21:24 +0000 (19:21 +0200)
commitb4ed9f86df441d7ac304f70cc711c257e7c8ebf1
treef4d7cb36366971a6397f1cc5ec0ee8217c196655
parent9927d60f4aadcecbd3143400d01ad4500438ea4f
mx6: Set shared override bit in PL310 AUX_CTRL register

Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

This was inspired by a patch from Catalin Marinas [1] and also from recent
discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring
suggested that bootloaders should initialize the cache.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html
[2] https://lkml.org/lkml/2015/2/20/199

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/include/asm/pl310.h