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(parent: 7395a72) | patch
Optimize barrier usage during Cortex-A57 power down
authorSoby Mathew <soby.mathew@arm.com>
Mon, 22 Sep 2014 11:15:26 +0000 (12:15 +0100)
committerSoby Mathew <soby.mathew@arm.com>
Wed, 29 Oct 2014 17:38:56 +0000 (17:38 +0000)
commitb1a9631d8110a2bcd458ec5809b50d5263a200ef
tree8fd89f21b24dfb9a0b6c00c0aa137547d50cfcd5tree | snapshot
parent7395a725ae74de70820d7b126ba1af727f39e263commit | diff
Optimize barrier usage during Cortex-A57 power down

This the patch replaces the DSB SY with DSB ISH
after disabling L2 prefetches during the Cortex-A57
power down sequence.

Change-Id: I048d12d830c1b974b161224eff079fb9f8ecf52d
lib/cpus/aarch64/cortex_a57.S diff | blob | history
Broadcom-s Trusted Firmware A