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clk: imx8mq: Define gates for pll1/2 fixed dividers
authorLeonard Crestez <leonard.crestez@nxp.com>
Wed, 16 Oct 2019 11:57:37 +0000 (11:57 +0000)
committerShawn Guo <shawnguo@kernel.org>
Fri, 25 Oct 2019 09:03:00 +0000 (17:03 +0800)
commitb04383b6a5588906ffd059a6a9f5344a9c6df58a
treecd4829d3487a4bee55052623e60d916131802b5btree | snapshot
parent8f2d3c1759d19232edf1e9ef43d40a44e31493d6commit | diff
clk: imx8mq: Define gates for pll1/2 fixed dividers

On imx8mq there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate but these gates are not currently defined in
the clock tree.

Add them between sys1/2_pll_out and the fixed dividers.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/clk/imx/clk-imx8mq.c diff | blob | history
include/dt-bindings/clock/imx8mq-clock.h diff | blob | history
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