arm64: cacheinfo: Remove CCSIDR-based cache information probing
authorWill Deacon <will.deacon@arm.com>
Fri, 10 Mar 2017 20:32:21 +0000 (20:32 +0000)
committerCatalin Marinas <catalin.marinas@arm.com>
Mon, 20 Mar 2017 16:16:54 +0000 (16:16 +0000)
commita8d4636f96ad075dc6d6af182b3de0b5498dc301
treeba0483ccb5c180e1f341b0ca5b7773941b959553
parent3689c75af2a3bc944826e6da663deee50c97d910
arm64: cacheinfo: Remove CCSIDR-based cache information probing

The CCSIDR_EL1.{NumSets,Associativity,LineSize} fields are only for use
in conjunction with set/way cache maintenance and are not guaranteed to
represent the actual microarchitectural features of a design.

The architecture explicitly states:

| You cannot make any inference about the actual sizes of caches based
| on these parameters.

Furthermore, CCSIDR_EL1.{WT,WB,RA,WA} have been removed retrospectively
from ARMv8 and are now considered to be UNKNOWN.

Since the kernel doesn't make use of set/way cache maintenance and it is
not possible for userspace to execute these instructions, we have no
need for the CCSIDR information in the kernel.

This patch removes the accessors, along with the related portions of the
cacheinfo support, which should instead be reintroduced when firmware has
a mechanism to provide us with reliable information.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/include/asm/cachetype.h
arch/arm64/kernel/cacheinfo.c