x86/Centaur: Report correct CPU/cache topology
authorDavid Wang <davidwang@zhaoxin.com>
Thu, 3 May 2018 02:32:46 +0000 (10:32 +0800)
committerThomas Gleixner <tglx@linutronix.de>
Sun, 13 May 2018 14:14:24 +0000 (16:14 +0200)
commita2aa578fec8c29436bce5e6c15e1e31729d539a3
treec81c1a8e4b4fad8bdf23ff42bebf8521ec88d0fb
parent807e9bc8e2fe6b4907f9f77fd073f7ef5073af29
x86/Centaur: Report correct CPU/cache topology

Centaur CPUs enumerate the cache topology in the same way as Intel CPUs,
but the function is unused so for. The Centaur init code also misses to
initialize x86_info::max_cores, so the CPU topology can't be described
correctly.

Initialize x86_info::max_cores and invoke init_cacheinfo() to make
CPU and cache topology information available and correct.

Signed-off-by: David Wang <davidwang@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: lukelin@viacpu.com
Cc: qiyuanwang@zhaoxin.com
Cc: gregkh@linuxfoundation.org
Cc: brucechang@via-alliance.com
Cc: timguo@zhaoxin.com
Cc: cooperyan@zhaoxin.com
Cc: hpa@zytor.com
Cc: benjaminpan@viatech.com
Link: https://lkml.kernel.org/r/1525314766-18910-4-git-send-email-davidwang@zhaoxin.com
arch/x86/kernel/cpu/centaur.c