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(parent: b689a83) | patch
drm/msm/a6xx: Send the right perf index value to GMU
authorSharat Masetty <smasetty@codeaurora.org>
Thu, 27 Sep 2018 16:46:22 +0000 (22:16 +0530)
committerRob Clark <robdclark@gmail.com>
Thu, 4 Oct 2018 00:24:54 +0000 (20:24 -0400)
commit9fb4bfd0be010371d3fdd2280e9d99f315382379
tree0f9aa5738480512e3593cfd321869bf70e8bc133tree | snapshot
parentb689a830f5264e3a53307ba468e376e9f95f15e0commit | diff
drm/msm/a6xx: Send the right perf index value to GMU

The index of the perf table was being set in the wrong bit position
in the register. With this fix, the GPU clock can be seen running at
desired frequency.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/adreno/a6xx_gmu.c diff | blob | history
John Crispins staging tree