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PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory...
authorBharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Tue, 9 Aug 2016 14:00:09 +0000 (19:30 +0530)
committerRob Herring <robh@kernel.org>
Tue, 30 Aug 2016 22:07:47 +0000 (17:07 -0500)
commit9cbbae2a62bce72c17aeb204efeec240f45c4f4f
tree8cdc2df6dc58695bab731f4fc7c14ed223ddade7tree | snapshot
parentc4dcd205ebabe730858fc0f33a6a9a09bcd53452commit | diff
PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space

Updating device tree documentation with prefetchable memory
sapce.
Configuration space shifted to 64-bit address space.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt diff | blob | history
John Crispins staging tree