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(parent: 807abb1) | patch
arm: socfpga: cache: Define cacheline size
authorMarek Vasut <marex@denx.de>
Sun, 14 Sep 2014 23:27:57 +0000 (01:27 +0200)
committerMarek Vasut <marex@denx.de>
Mon, 6 Oct 2014 15:46:50 +0000 (17:46 +0200)
commit9ca2116ce49449602eb9e2f8a0cafe811bcc3086
tree61cd055ff4710141c57d53e2d574c433a5176b7dtree | snapshot
parent807abb18f1376bcd674540e374f2ab7503caea51commit | diff
arm: socfpga: cache: Define cacheline size

The Cortex-A9 has 32-byte long L1 cachelines. Define this value.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
include/configs/socfpga_cyclone5.h diff | blob | history
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