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ath79: fix PCIe initialization on AR934x
authorINAGAKI Hiroshi <musashino.open@gmail.com>
Fri, 26 Apr 2024 14:53:58 +0000 (23:53 +0900)
committerHauke Mehrtens <hauke@hauke-m.de>
Sun, 28 Jul 2024 16:47:56 +0000 (18:47 +0200)
commit98f73552a78e1c6d825dc3ba9845b4c63c3f16c6
tree268ed33c531c57c732157e4078066b017bd1ff60tree | snapshot
parent08705d44813c0f9208b6e9c52deaded7ba914a94commit | diff
ath79: fix PCIe initialization on AR934x

Fix PCIe initialization on AR934x by clearing PLL_PWD bit in addition to
PPL(PLL?)_RESET bit of AR724x.

Refresh patches by `make target/linux/refresh`.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/15432
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
target/linux/ath79/patches-6.6/317-MIPS-pci-ar724x-clear-power-down-of-pll-on-AR934x.patch [new file with mode: 0644] blob
target/linux/ath79/patches-6.6/330-missing-registers.patch diff | blob | history
target/linux/ath79/patches-6.6/331-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch diff | blob | history
target/linux/ath79/patches-6.6/332-ath79-sgmii-config.patch diff | blob | history
target/linux/ath79/patches-6.6/360-MIPS-ath79-export-UART1-reference-clock.patch diff | blob | history
Staging tree of David Bauer