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(parent: 93a15b5) | patch
drm/i915/gvt: add write handler for mmio mbctl
authorPei Zhang <pei.zhang@intel.com>
Mon, 20 Mar 2017 15:49:19 +0000 (23:49 +0800)
committerZhenyu Wang <zhenyuw@linux.intel.com>
Mon, 20 Mar 2017 08:43:39 +0000 (16:43 +0800)
commit975629c3f76ce3d86e1f943db9847e0312a98daf
treedce918c19c9c1511d6730b9c8c78797c432647e0tree | snapshot
parent93a15b58cfb8a24e666ffca432f19fe65c1cd7d1commit | diff
drm/i915/gvt: add write handler for mmio mbctl

Guest will write mmio mbctl which need a special handler in gvt to
clear the bit 4 to inidcate the write operation success.

V2: use bit definition macro to make code readable.

Signed-off-by: Pei Zhang <pei.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
drivers/gpu/drm/i915/gvt/handlers.c diff | blob | history
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