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zynqmp: pm: Correct WDT clock database
authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Tue, 4 Sep 2018 12:03:19 +0000 (17:33 +0530)
committerSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Tue, 4 Sep 2018 12:03:19 +0000 (17:33 +0530)
commit96cd17f49d9a40ca3620b05d4e5cd09b8205f59a
tree5715f4d48ab6749fd0bacbcec5d0bcae1bceb3fdtree | snapshot
parent6ad42b989d3c8352f15bb9d14dd403cd15bb652ecommit | diff
zynqmp: pm: Correct WDT clock database

WDT used by APU is FPD_WDT. FPD WDT clock is controlled by
FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock
database.

As per FPD_SLCR.WDT_CLK_SEL register, there can be only two
parents of WDT clock not three. Fix the same by correcting it's
parents in clock database.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>
plat/xilinx/zynqmp/pm_service/pm_api_clock.c diff | blob | history
plat/xilinx/zynqmp/zynqmp_def.h diff | blob | history
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