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(parent: a3d9103) | patch
drm/amd/display: Fix bug use wrong pp interface
authorRex Zhu <Rex.Zhu@amd.com>
Thu, 16 Aug 2018 03:36:38 +0000 (11:36 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 27 Aug 2018 16:09:41 +0000 (11:09 -0500)
commit9650205a32e7f69c9846a205351e307ea525c1e7
tree40e2846419a1788011722692bb53b1d3a18c18b4tree | snapshot
parenta3d9103ebfa03824d255060fc2c11ac94e3ef441commit | diff
drm/amd/display: Fix bug use wrong pp interface

Used wrong pp interface, the original interface is
exposed by dpm on SI and paritial CI.

Pointed out by Francis David <david.francis@amd.com>

v2: dal only need to set min_dcefclk and min_fclk to smu.
    so use display_clock_voltage_request interface,
    instand of update all display configuration.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c diff | blob | history
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