drm/amd/display: Modified set bandwidth sequence.
authorYongqiang Sun <yongqiang.sun@amd.com>
Tue, 27 Feb 2018 20:06:31 +0000 (15:06 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 14 Mar 2018 20:08:44 +0000 (15:08 -0500)
commit8e437c799158be80aa1ae27f362e30081e2a1e9f
tree83948fc1b5666c03948d592c508d3aa89920334a
parentd03f3f6304336b85737d77393d55cd4d89154c72
drm/amd/display: Modified set bandwidth sequence.

This change make sure bandwidth is set properly.
For increase bandwidth, set bandwidth before backend
and front end programming.
For decrease bandwidth, set bandwidth after.
To avoid smu hang when reboot and dpms due to 0 disp clk,
keep min disp clock as 100Mhz.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c