drm/i915: disable GTT cache for 2M pages
authorMatthew Auld <matthew.auld@intel.com>
Fri, 6 Oct 2017 22:18:23 +0000 (23:18 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Sat, 7 Oct 2017 09:11:54 +0000 (10:11 +0100)
commit8cb0983678e05939457d867e09bddb6883db5268
tree64b17f86907191c5a93d025745f069aca336d65d
parent9a6330cff9b4b0691c7554fe873b09e7f6d377a9
drm/i915: disable GTT cache for 2M pages

When SW enables the use of 2M/1G pages, it must disable the GTT cache.

v2: don't disable for Cherryview which doesn't even support 48b PPGTT!

v3: explicitly check that the system does support 2M/1G pages

v4: split WA and decision logic

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171006145041.21673-12-matthew.auld@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171006221833.32439-11-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/intel_pm.c