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(parent: 9450526) | patch
cxgb3: fix Gen2 pci default settings
authorDivy Le Ray <divy@chelsio.com>
Thu, 30 Jul 2009 21:23:39 +0000 (21:23 +0000)
committerDavid S. Miller <davem@davemloft.net>
Sun, 2 Aug 2009 19:23:40 +0000 (12:23 -0700)
commit88e7b76ef7cf939a0cf23a1902030211b20837fe
tree7bfd1742802e9cdb5539a0320f2440b524a3f71etree | snapshot
parent9450526ac7bd74edf1ee030841d8078c6db6ca0bcommit | diff
cxgb3: fix Gen2 pci default settings

Modify control register settings to accommodate the bridge's max read
requset size.

Signed-off-by: Divy Le Ray <divy@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/cxgb3/t3_hw.c diff | blob | history
John Crispins staging tree