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MPC85xx: TQM8548: fix SDRAM timing for 533 MHz
authorWolfgang Grandegger <wg@grandegger.com>
Wed, 11 Feb 2009 17:38:23 +0000 (18:38 +0100)
committerAndy Fleming <afleming@freescale.com>
Tue, 17 Feb 2009 00:06:00 +0000 (18:06 -0600)
commit88b0e88d186479349e5a2b771e82775109e10fb4
tree57005d81dfa792dd313496dc1c44930b7219a56ftree | snapshot
parenta865bcdac89278cac4dfc07dec8299403110499dcommit | diff
MPC85xx: TQM8548: fix SDRAM timing for 533 MHz

According to new TQM8548 timing specification:
Refresh Recovery: 34 -> 53 clocks
CKE pulse width:  1 -> 3 cycles
Window for four activities: 13 -> 14 cycles

Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
board/tqc/tqm85xx/sdram.c diff | blob | history
Broadcom-s U-Boot