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(parent: f2032d4) | patch
drm: micro optimise cache flushing
authorDave Airlie <airlied@redhat.com>
Wed, 19 Sep 2012 01:12:41 +0000 (11:12 +1000)
committerDave Airlie <airlied@gmail.com>
Wed, 19 Sep 2012 09:59:26 +0000 (19:59 +1000)
commit87229ad9de079cb12ee09a3dc16113c390b729d5
tree3f2a198c4c69346656611fe284c17f8a42080541tree | snapshot
parentf2032d413a2d47089f2b3f8fdd0e344a04de8195commit | diff
drm: micro optimise cache flushing

We hit this a lot with i915 and although we'd like to engineer things to hit
it a lot less, this commit at least makes it consume a few less cycles.

from something containing
movzwl 0x0(%rip),%r10d
to
add    %r8,%rdx

I only noticed it while using perf to profile something else.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/drm_cache.c diff | blob | history
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