pinctrl: qcom: ssbi-gpio: hardcode IRQ counts
authorBrian Masney <masneyb@onstation.org>
Fri, 8 Feb 2019 02:16:21 +0000 (21:16 -0500)
committerLinus Walleij <linus.walleij@linaro.org>
Wed, 13 Feb 2019 08:21:28 +0000 (09:21 +0100)
commit86291029e97eaf6a9c2ed43e7968ba8cf9f9f3b7
tree37d570fba121cb8188d9ba22c19012e628de178d
parente7dc6af82c284b8c79a0be5d2c9b555c3d793a3e
pinctrl: qcom: ssbi-gpio: hardcode IRQ counts

The probing of this driver calls platform_irq_count, which will
setup all of the IRQs that are configured in device tree. In
preparation for converting this driver to be a hierarchical IRQ
chip, hardcode the IRQ count based on the hardware type so that all
the IRQs are not configured immediately and are configured on an
as-needed basis later in the boot process. This change will also
allow for the removal of the interrupts property later in this
patch series once the hierarchical IRQ chip support is in.

This patch also removes the generic qcom,ssbi-gpio OF match since we
don't know the number of pins. All of the existing upstream bindings
already include the more-specific binding.

This change was tested on an APQ8060 DragonBoard.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c