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(parent: 6ca9da4) | patch
85xx: Add support for e500mc cache stashing
authorKumar Gala <galak@kernel.crashing.org>
Thu, 19 Mar 2009 07:53:01 +0000 (02:53 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Tue, 5 Jan 2010 19:49:02 +0000 (13:49 -0600)
commit82fd1f8da9add2d74532cf78d224485f0042d00d
tree40c31ab6b1538c54882294ad7f2752ca60097910tree | snapshot
parent6ca9da4d42aeb43df5ef29f7d0518009df583b2fcommit | diff
85xx: Add support for e500mc cache stashing

The e500mc core supports the ability to stash into the L1 or L2 cache,
however we need to uniquely identify the caches with an id.

We use the following equation to set the various stash-ids:

32 + coreID*2 + 0(L1) or 1(L2)

The 0 (for L1) or 1 (for L2) matches the CT field used be various cache
control instructions.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
cpu/mpc85xx/cpu_init.c diff | blob | history
cpu/mpc85xx/fdt.c diff | blob | history
cpu/mpc85xx/release.S diff | blob | history
cpu/mpc85xx/start.S diff | blob | history
Broadcom-s U-Boot