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(parent: dc326f6) | patch
drm/amd/display: Link training TPS1 workaround
authorMartin Leung <martin.leung@amd.com>
Wed, 12 Feb 2020 20:38:51 +0000 (15:38 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 25 Feb 2020 16:08:35 +0000 (11:08 -0500)
commit82054678aeb66907acd63df7d1d5f9556e29a5cc
tree6b2829394a80211919696195cfeb4fd1d384b5ectree | snapshot
parentdc326f61c51df641fbf4f42303e860f53ea163c1commit | diff
drm/amd/display: Link training TPS1 workaround

[Why]
Previously implemented early_cr_pattern was link level but the whole
asic should be affected.

[How]
 - change old link flag to dc level
 - new bit in dc->work_arounds set by DM

Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dc.h diff | blob | history
drivers/gpu/drm/amd/display/dc/dc_link.h diff | blob | history
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