ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value
authorLokesh Vutla <lokeshvutla@ti.com>
Mon, 16 Feb 2015 04:45:56 +0000 (10:15 +0530)
committerTom Rini <trini@ti.com>
Mon, 16 Feb 2015 17:41:40 +0000 (12:41 -0500)
commit802bb57a584db2202a47d41ac730fe76ddeb4f33
tree499ccc1cbbb52182227112a9fb7eb37fc7bfafe9
parentaa8ac43645243b69faf0e81fab5f0d6fcf4285cf
ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value

The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/cpu/armv7/omap-common/emif-common.c
arch/arm/cpu/armv7/omap5/sdram.c
arch/arm/include/asm/emif.h
board/ti/beagle_x15/board.c