powerpc/85xx: Fix synchronization of timebase on MP boot
authorKumar Gala <galak@kernel.crashing.org>
Sun, 13 Mar 2011 15:55:53 +0000 (10:55 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Tue, 15 Mar 2011 06:25:51 +0000 (01:25 -0500)
commit7afc45ad7d9493208d89072cbb78a5bfc8034b59
tree233adc7346c3ec0f4e84cb8637ad79d9b43a5bba
parentcc1dd33f273f8c96cbd7539b4a2d1d7aa12773cd
powerpc/85xx: Fix synchronization of timebase on MP boot

There is a small ordering issue in the master core in that we need to
make sure the disabling of the timebase in the SoC is visible before we
set the value to 0.  We can simply just read back the value to
synchronizatize the write, before we set TB to 0.

Reported-by: Dan Hettena
Tested-by: Dan Hettena
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/cpu/mpc85xx/mp.c