projects / openwrt / staging / blogic.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: c38864a) | patch
clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
authorTuomas Tynkkynen <ttynkkynen@nvidia.com>
Wed, 13 May 2015 14:58:43 +0000 (17:58 +0300)
committerThierry Reding <treding@nvidia.com>
Thu, 16 Jul 2015 08:40:20 +0000 (10:40 +0200)
commit79cf95c763a11d4b365cd5a627fd1ab4dca67890
treec314059d2be0ef328cb28b533cb2e66fbe414b97tree | snapshot
parentc38864a703f3fe50e2b87883a0def392dd5bf26fcommit | diff
clk: tegra: Add the DFLL as a possible parent of the cclk_g clock

The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra-super-gen4.c diff | blob | history
John Crispins staging tree